In the design and manufacture of ASIC (Application specific integrated circuit) chips and microprocessor chips it is conventional practice to provide the chip designer with a library of conventional circuits from which to chose and generate his/her design. The chip designer chooses from this library the necessary circuits and connects them to form the desired chip configuration. In the case of microprocessors the designs and parameters of the library circuits are fixed thus imposing certain constraints on the chip designer. In the case of ASIC chips not only are the designs fixed but also the rules of wiring are fixed thus imposing additional constraints. Thus the designer is constrained by the circuit design and in the case of ASIC chips the rules in using the various circuits.
One of the library circuits that can be used by a chip designer is a phase locked loop circuit. Phase locked loops (PLLs) are widely used in many different applications. They are used to perform two or three different functions. A principal function is to lock or align the output clock of a circuit with the clock input. Another function is to multiply (i.e. increase) or divide (i.e. decrease) the output frequency of a circuit with respect to the input frequency. Another function of a phase locked loop is to provide clock recovery, i.e. to attenuate the input jitter associated with input signals and recover clock from jittery input data.
Local oscillators are well known devices and have been used in many applications, including PLLs. Most local oscillators are single ended or differential CMOS, e.g., single ended CMOS, differential CMOS and bipolar. As networking and communication systems are playing increasingly more important roles in the present information age, demands for high speed local oscillators are significantly increased to keep up with the speed of these systems.
One of the difficult elements of a PLL is the buffer circuit used to take the outputs from a local oscillator and produce a signal which is nearly rail-to-rail and can drive a load consisting of divider circuits and possibly fan outs to other digital circuits. This means that the circuit requires a high gain bandwidth to support the frequency of operation and also the gain required to get the signal from what is normally much less than full rail to as close to rail-to-rail as possible.
It can be seen then that there is a need for a method and apparatus for providing a high speed buffer with high gain bandwidth and rail-to-rail operation.